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PD - 91666B
IRFE130 REPETITIVE A ALANCHE AND dv/dt RATED V JANTX2N6796U HEXFET TRANSISTORS JANTXV2N6796U SURFACE MOUNT (LCC-18) [REF:MIL-PRF-19500/557] 100V, N-CHANNEL
Product Summary
Part Number IRFE130 BVDSS 100V RDS(on) 0.18 ID 8.0A
The leadless chip carrier (LCC) package represents the logical next step in the continual evolution of surface mount technology. Desinged to be a close replacement for the TO-39 package, the LCC will give designers the extra flexibility they need to increase circuit board density. International Rectifier has engineered the LCC package to meet the specific needs of the power market by increasing the size of the bottom source pad, thereby enhancing the thermal and electrical performance. The lid of the package is grounded to the source to reduce RF interference.
LCC-18
Features:
! ! ! ! ! ! ! !
Surface Mount Small Footprint Alternative to TO-39 Package Hermetically Sealed Dynamic dv/dt Rating Avalanche Energy Rating Simple Drive Requirements Light Weight
Absolute Maximum Ratings
Parameter
ID @ VGS = 10V, TC = 25C ID @ VGS = 10V, TC = 100C I DM PD @ TC = 25C VGS EAS IAR EAR dv/dt TJ T STG Continuous Drain Current Continuous Drain Current Pulsed Drain Current Max. Power Dissipation Linear Derating Factor Gate-to-Source Voltage Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Operating Junction Storage Temperature Range Pckg. Mounting Surface Temp. Weight For footnotes refer to the last page 8.0 5.0 32 25 0.17 20 134 8.3 -55 to 150 300 (for 5 S) 0.42(typical)
Units A
W
W/C
V mJ A mJ V/ns
o
C
g
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1/17/01
IRFE130
Electrical Characteristics
Parameter
BVDSS BV DSS/TJ RDS(on) VGS(th) gfs IDSS
@ Tj = 25C (Unless Otherwise Specified) Min
100 -- -- -- 2.0 3.0 -- -- -- -- -- -- -- -- -- -- -- --
Typ Max Units
-- 0.11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 6.1 -- -- 0.18 0.207 4.0 -- 25 250 100 -100 29 6.5 17 30 75 40 45 -- V V/C V S( ) A nA nC
Test Conditions
VGS = 0V, ID = 1.0mA Reference to 25C, ID = 1.0mA VGS = 10V, ID =5.0A VGS =10V, ID =8.0A VDS = VGS, ID =250A VDS > 15V, IDS =5.0A VDS=80V, VGS=0V VDS =80V VGS = 0V, TJ = 125C VGS =20V VGS =-20V VGS =10V, ID= 8.0A VDS =50V VDD =50V, ID =8.0A, RG =7.5
Drain-to-Source Breakdown Voltage Temperature Coefficient of Breakdown Voltage Static Drain-to-Source On-State Resistance Gate Threshold Voltage Forward Transconductance Zero Gate Voltage Drain Current
IGSS IGSS Qg Qgs Qgd td(on) tr td(off) tf LS + LD
Gate-to-Source Leakage Forward Gate-to-Source Leakage Reverse Total Gate Charge Gate-to-Source Charge Gate-to-Drain (`Miller') Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Inductance
ns nH
Measured from the center of drain pad to center of source pad VGS = 0V, VDS =25V f = 1.0MHz
Ciss Coss Crss
Input Capacitance Output Capacitance Reverse Transfer Capacitance
-- -- --
660 260 51
-- --
pF
Source-Drain Diode Ratings and Characteristics
Parameter
IS ISM VSD t rr QRR ton Continuous Source Current (Body Diode) Pulse Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Forward Turn-On Time
Min Typ Max Units
-- -- -- -- -- -- -- -- -- -- 8.0 32 1.5 300 970
Test Conditions
A
V nS c Tj = 25C, IS =8.0A, VGS = 0V Tj = 25C, IF =8.0A, di/dt 100A/s VDD 50V
Intrinsic turn-on time is negligible. Turn-on speed is substantially controlled by LS + LD.
Thermal Resistance
Parameter
RthJC RthJ-PCB Junction to Case Junction to PC Board
Min Typ Max Units
-- -- -- -- 5.0 C/W 19" "
Test Conditions
Soldered to a copper clad PC board
For footnotes refer to the last page
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IRFE130
100
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
10
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM4.5V TOP
100
10
VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V BOTTOM 4.5V TOP
4.5V
4.5V
1
1
0.1 0.1
20s PULSE WIDTH TJ = 25C
1 10 100
0.1 0.1
20s PULSE WIDTH TJ = 150 C
1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
TJ = 25 C
10
RDS(on) , Drain-to-Source On Resistance (Normalized)
100
2.5
8.0 A ID = 7.4A
I D , Drain-to-Source Current (A)
2.0
TJ = 150 C
1.5
1.0
1
0.5
0.1
V DS = 50V 20s PULSE WIDTH 4 5 6 7 8 9 10
VGS , Gate-to-Source Voltage (V)
0.0 -60 -40 -20 0
V = 10V GS
20 40 60 80 100 120 140 160
TJ , Junction Temperature ( C)
Fig 3.
Typical Transfer Characteristics
Fig 4.
Normalized On-Resistance Vs. Temperature
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IRFE130
1200
1000
VGS , Gate-to-Source Voltage (V)
VGS = 0V, f = 1MHz Ciss = Cgs + Cgd , Cds SHORTED Crss = Cgd Coss = Cds + Cgd
20
8.0A ID = 7.4 A
16
V DS = 80V V DS = 50V V DS = 20V
C, Capacitance (pF)
800
Ciss Coss
12
600
8
400
200
4
Crss
1 10 100
0
0
FOR TEST CIRCUIT SEE FIGURE 13
0 6 12 18 24 30
VDS , Drain-to-Source Voltage (V)
QG , Total Gate Charge (nC)
Fig 5. Typical Capacitance Vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge Vs. Gate-to-Source Voltage
100
1000
ISD , Reverse Drain Current (A)
TJ = 25 C T J = 150 C
OPERATION IN THIS AREA LIMITED BY RDS(on)
10
ID , Drain Current (A)
100 10us 10 100us 1ms 1 10ms
1
0.1 0.2
VGS = 0 V
0.8 1.4 2.0 2.6
0.1
TC = 25 C TJ = 150 C Single Pulse
1 10 100 1000
VSD ,Source-to-Drain Voltage (V)
V DS , Drain-to-Source Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 8. Maximum Safe Operating Area
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IRFE130
10.0
V DS
8.0
RD
I D , Drain Current (A)
VGS RG
D.U.T.
+
6.0
-V DD
10V
4.0
Pulse Width 1 s Duty Factor 0.1 %
2.0
Fig 10a. Switching Time Test Circuit
VDS
0.0
90%
25 50 75 100 125 150
TC , Case Temperature ( C)
10% VGS
Fig 9. Maximum Drain Current Vs. Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
100
Thermal Response (Z thJC )
10 D = 0.50 1 0.20 0.10 0.05 0.1 0.02 0.01 P DM t1 SINGLE PULSE (THERMAL RESPONSE) t2 Notes: 1. Duty factor D = t 1 / t 2 2. Peak T J = P DM x Z thJC + TC 0.001 0.01 0.1 1
0.01 0.00001
0.0001
t1 , Rectangular Pulse Duration (sec)
Fig 11.
Maximum Effective Transient Thermal Impedance, Junction-to-Case
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IRFE130
EAS , Single Pulse Avalanche Energy (mJ)
400
TOP
300
15V
BOTTOM
ID 3.3A 5.0A 8.0A
VDS
L
DRIVER
200
RG
D.U.T
IAS tp
+ V - DD
A
10V 20V
0.01
100
Fig 12a. Unclamped Inductive Test Circuit
0
25
50
75
100
125
150
V(BR)DSS tp
Starting TJ , Junction Temperature ( C)
Fig 12c. Maximum Avalanche Energy Vs. Drain Current
I AS
Fig 12b.
Unclamped Inductive Waveforms
Current Regulator Same Type as D.U.T.
50K
QG
12V
.2F .3F
10 V
QGS VG QGD
VGS
3mA
D.U.T.
+ V - DS
Charge
IG
ID
Current Sampling Resistors
Fig 13a. Basic Gate Charge Waveform
Fig 13b. Gate Charge Test Circuit
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IRFE130
Repetitive Rating; Pulse width limited by
maximum junction temperature. VDD = 50V, starting TJ = 25C, Peak IL =8.0A,
Foot Notes:
ISD 8.0A, di/dt 480A/s,
VDD 100V, TJ 150C Suggested RG =7.5 Pulse width 300 s; Duty Cycle 2%
Case Outline and Dimensions -- LCC-18
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 IR EUROPEAN REGIONAL CENTRE: 439/445 Godstone Rd, Whyteleafe, Surrey CR3 OBL, UK Tel: ++ 44 (0)20 8645 8000 IR CANADA: 15 Lincoln Court, Brampton, Ontario L6T3Z2, Tel: (905) 453 2200 IR GERMANY: Saalburgstrasse 157, 61350 Bad Homburg Tel: ++ 49 (0) 6172 96590 IR ITALY: Via Liguria 49, 10071 Borgaro, Torino Tel: ++ 39 011 451 0111 IR JAPAN: K&H Bldg., 2F, 30-4 Nishi-Ikebukuro 3-Chome, Toshima-Ku, Tokyo 171 Tel: 81 (0)3 3983 0086 IR SOUTHEAST ASIA: 1 Kim Seng Promenade, Great World City West Tower, 13-11, Singapore 237994 Tel: ++ 65 (0)838 4630 IR TAIWAN:16 Fl. Suite D. 207, Sec. 2, Tun Haw South Road, Taipei, 10673 Tel: 886-(0)2 2377 9936 Data and specifications subject to change without notice. 9/00
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